Multiplexer
This
component contains a multiplexer for boolean values. The multiplexer routes one
of the input values to the output connector. The selected input connector
depends on the address read from the address inputs.
The component
has an internal address latch. This latch is activated if the optional
connector 'Enable Latch Address' is activated. During true condition at this
input the current address is used. A change to false condition latches the
address. During false condition at this input the latched address is used. The
latch is bypassed if the optional connector 'Enable Latch Address' is
deactivated.
The component
also has an internal output latch. This latch is activated if the connector
'Enable Latch Output' is activated. During true condition at this input the
current addressed input value is used. A change to false condition latches the
output value. During false condition at this input the latched output value is
used. The latch is bypassed if the optional connector 'Enable Latch Output' is
deactivated.
If an input
is addressed which does not exist (e.g. the 15th input is selected but the
component has only 14 inputs) the reset value is used.
- Up to 16 inputs.
- The all inputs and
outputs are negatable.
- The 'Latch Address
Input' and 'Latch Output' inputs are level or edge sensitive.
- Activate or
deactivate the optional 'Latch Address Input' and 'Latch Output' inputs
(deactivated connectors are hidden).
- The component is
rotatable.
Address A
|
Address B
|
Input A
|
Input B
|
Input C
|
Input D
|
Output
|
|
False
|
False
|
False
|
X
|
X
|
X
|
False
|
|
False
|
False
|
True
|
X
|
X
|
X
|
True
|
|
True
|
False
|
X
|
False
|
X
|
X
|
False
|
|
True
|
False
|
X
|
True
|
X
|
X
|
True
|
|
False
|
True
|
X
|
X
|
False
|
X
|
False
|
|
False
|
True
|
X
|
X
|
True
|
X
|
True
|
|
True
|
True
|
X
|
X
|
X
|
False
|
False
|
|
True
|
True
|
X
|
X
|
X
|
True
|
True
|
The truth table shows a 4-input multiplexer.
Enable Output Latch
|
Address A
|
Input A
|
Input B
|
Output(t)
|
|
True
|
False
|
False
|
X
|
False
|
|
True
|
False
|
True
|
X
|
True
|
|
True
|
True
|
X
|
False
|
False
|
|
True
|
True
|
X
|
True
|
True
|
|
False
|
X
|
X
|
X
|
Output(t-1)
|
The truth table shows a 2-input multiplexer
width output latch. The enable input of the output latch input is level
sensitive.
Demultiplexer
This
component contains a demultiplexer for boolean values. The demultiplexer routes
the input value to one of the output connectors. The selected output connector
depends on the address read from the address inputs.
The component
has an internal address latch. This latch is activated if the optional
connector 'Enable Latch Address' is activated. During true condition at this
input the current address is used. A change to false condition latches the
address. During false condition at this input the latched address is used. The
latch is bypassed if the optional connector 'Enable Latch Address' is
deactivated.
The component
also has an internal output latch. This latch is activated if the connector
'Enable Latch Output' is activated. During true condition at this input the
latch is bypassed. A change to false condition latches the last output values.
During false condition at this input the latched output values are used. The
latch is bypassed if the optional connector 'Enable Latch' is deactivated.
- Up to 16 outputs.
- The all inputs and
outputs are negatable.
- The 'Latch Address
Input' input are level or edge sensitive.
- Activate or
deactivate the optional 'Latch Address Input' (deactivated connectors are
hidden).
- The component is
rotatable.
Address A
|
Address B
|
Input
|
Output A
|
Output B
|
Output C
|
Output D
|
|
X
|
X
|
False
|
False
|
False
|
False
|
False
|
|
False
|
False
|
True
|
True
|
False
|
False
|
False
|
|
True
|
False
|
True
|
False
|
True
|
False
|
False
|
|
False
|
True
|
True
|
False
|
False
|
True
|
False
|
|
True
|
True
|
True
|
False
|
False
|
False
|
True
|
The truth table shows a 4-output demultiplexer
(or a 2-to-4 decoder).
Enable Output Latch
|
Address A
|
Input
|
Output A(t)
|
Output B(t)
|
|
True
|
X
|
False
|
False
|
False
|
|
True
|
False
|
True
|
True
|
False
|
|
True
|
True
|
True
|
False
|
True
|
|
False
|
X
|
X
|
Output A(t-1)
|
Output B(t-1)
|
The truth table shows a 2-input multiplexer
width output latch. The enable input of the output latch input is level
sensitive.
